This invention relates generally to chip design, and more particularly, to inserting components, such as decoupling capacitors, in a hierarchical chip design.
As semiconductor technologies become more complex and condensed, if becomes difficult to use simple algorithms to insert components, such as decoupling capacitors, into chip designs, e.g., cell-based Very Large Scale Integration (VLSI) chip designs, without violating manufacturing ground rules or incurring numerous iterations of checking and manual tweaking. In a very eel I-based hierarchical VLSI, design, decoupling capacitors, also referred to as decaps, are usually inserted at each level of hierarchy and brought together at the chip or parent level. This leads to undesired interactions between those hierarchies at the top level and requires a good amount of debugging and ripping up.
Also, the latest Complementary Metal Oxide Semiconductor (CMOS) technologies are very sensitive to silicon densities and uniformity of silicon layers, which has led to the creation of specialized ground rules to control process variations across the chip's area, also known, as Across Chip Line Variation (ACLV). Some of these rules are very complex and can be triggered by the interaction of different circuit types.
There is thus a need for a technique for inserting components into a hierarchical chip design without violating ground rules for controlling process variations across the chip.